Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize conductive vias and conduct lines to connect structures (e.g., gates, drain regions, source regions) and other conductive lines. A conductive via is typically a metal or conductive plug which extends through an insulative or semiconductor layer. A barrier layer is used to reduce diffusion and electromigration in the via and conductive lines. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, it is characteristic of metals at very high current density and temperatures of 100° C. or more.
Electromigration failures have been described by Stanley Wolf, Ph.D. in Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, Calif., Vol. 2, pp. 264–65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductive line leads to an accumulation of vacancies, forming voids in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductive line.
According to one conventional metal layer design, the metal layer (e.g., metal 1, metal 2, etc.) includes conductive lines and dielectric material. The conductive lines are situated in the dielectric material and are connected to conductive vias extending to the substrate and other metal layers. The conductive lines and conductive vias can include copper to achieve the advantage of reduced resistivity.
Copper conductive lines can be formed according to a damascene process. The damascene process forms trenches in the dielectric material associated with the metal layers. The walls of the trenches are covered with a barrier material and copper seed layer is deposited over the barrier material. The copper seed layer provides an active surface region for enhancing adhesion of the copper to the barrier layer. The remainder of the trenches is filled with copper to complete the conductive lines.
After the trench is filled, the copper conductive line as well as the dielectric material is covered with a barrier layer. A dielectric layer (e.g., an interlevel dielectric layer (ILD)) is provided over the barrier layer to isolate the metal layer from other layers.
Conventional damascene processes often fill the trench by electroplating the copper seed layer. According to such a process, copper ions are electrically attracted to the surface of the seed layer during deposition by electroplating. The copper seed layer generally does not reduce or eliminate copper diffusion during electromigration because it is made of the same material as the copper conductive line.
Generally, the barrier material is a nitride material, such as silicon nitride (SiNx). One conventional form of suitable barrier material is Si3N4 deposited by chemical vapor deposition (CVD). The interface between the barrier material above the conductive line and the dielectric layer (the ILD) above the barrier layer can be susceptible to metal diffusion and electromigration. This susceptibility is particularly important when copper conductive lines are utilized. In addition, adhesion at this interface can be poor.
As conductive lines and barrier layers become smaller, barrier layers have become thinner. Thin barrier layers are desirable to reduce the resistivity of conductive vias. However, thinner barrier layers are more susceptible to electromigration and diffusion issues.
Thus, there is a need for an interface between the conductive line and dielectric layer that is more resistant to copper diffusion and less susceptible to electromigration. Further, there is a need for better adhesion at an interface between the conductive line and the dielectric layer. Even further, there is a need for a method of providing an interface for a copper line and dielectric layer that is less susceptible to electromigration and diffusion problems. Further, there is a need to optimize the barrier layer to increase electromigration resistance. Even further, there is a need for a method of optimizing a silicon nitride barrier layer to have improved resistance to electromigration and diffusion and to provide increased adhesion.